Fedachat V. 4 | Hilo de no postear

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-- Company: Codechordas
-- Engineer: Gnomechordas
-- 
-- Create Date:    12:57:21 10/06/2015 
-- Design Name:   

-- Module Name:    FIR_FSMD_SL - Behavioral 
-- Project Name:  Otegi askatu!
-- Target Devices: Arnaldo Otegi
-- Tool versions: Ernai
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
package IR is

type ImpulseResponse is array(7 downto 0) of signed(9 downto 0);
end package IR;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.IR.all;


entity FIR_FSMD_SL is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  

       x : in  signed (9 downto 0);
       h : in   ImpulseResponse;
       y : out  signed (21 downto 0));
end FIR_FSMD_SL;

architecture Behavioral of FIR_FSMD_SL is
 type matrix is array(7 downto 0) of signed(9 downto 0);
 type matrix_out is array(7 downto 0) of signed(19 downto 0);
 signal buffer_x : matrix;
 signal y_temp : matrix_out;
 signal sum1_1,sum1_2,sum1_3,sum1_4 :signed(19 downto 0);
 signal sum2_1,sum2_2 :signed(20 downto 0);

begin
	process(clk,reset)
	begin
	if reset = '1' then
		
	for i in 0 to 7 loop
	
	y_temp(i) <= (others => '0');
	buffer_x(i) <= (others => '0');
	end loop;
	sum1_1 <=  (others => '0');
	sum1_2 <=  (others => '0');
	sum1_3 <=  (others => '0');
	sum1_4 <=  (others => '0');
	sum2_1 <=  (others => '0');
	sum2_2 <=  (others => '0');
	y <=  (others => '0');
	
	
elsif clk'event and clk = '1' then
		y_temp(0) <= x*h(0);
		y_temp(1) <= buffer_x(7)*h(1);
		y_temp(2) <= buffer_x(6)*h(2);
		y_temp(3) <= buffer_x(5)*h(3);
		y_temp(4) <= buffer_x(4)*h(4);
		y_temp(5) <= buffer_x(3)*h(5);
		y_temp(6) <= buffer_x(2)*h(6);
		y_temp(7) <= buffer_x(1)*h(7);
		buffer_x(6 downto 0)<= buffer_x(7 downto 1);
		buffer_x(7) <= x;
		sum1_1 <=to_signed(to_integer(y_temp(0)+y_temp(1)),20);
		sum1_2 <=to_signed(to_integer(y_temp(2)+y_temp(3)),20);
		sum1_3 <=to_signed(to_integer(y_temp(4)+y_temp(5)),20);
		sum1_4 <=to_signed(to_integer(y_temp(6)+y_temp(7)),20);
		sum2_1 <=to_signed(to_integer(sum1_1 + sum1_2),21);
		sum2_2 <=to_signed(to_integer(sum1_3 + sum1_4),21);
		y <= to_signed(to_integer(sum2_1+sum2_2),22);
end if;
end process;

	
	
	

end Behavioral;